This application incorporates by reference Taiwanese application Serial No. 088115691, Filed Sep. 10, 1999.
1. Field of Invention
The present invention relates to a FIFO (first in first out) controlling method. More particularly, the present invention relates to a controlling method of a FIFO array used for transmitting signals between different devices.
2. Description of Related Art
FIG. 1 schematically illustrates a system block diagram of a conventional computer. In general, a central process unit (CPU) is connected to a north bridge chipset (NB) 104, and the NB 104 is further connected to memory 106 and a peripheral component interconnect (PCI) bus 108. The PCI bus 108 is then connected to a south bridge chipset (SB) having integrated disk electronics (IDE) interfaces 112 through which the SB can connect to IDE compatible devices, such as a hard disk 114.
Data transmission between various devices are usually controlled by PCI bus 108, IDE interface 112, south bridge chipset 110 and north bridge chipset 104. Taking data transmission between a memory 106 and a hard disk 114 as an example, when data are transferred from the hard disk 114 to the memory 106, a message must send to the memory 106 through the IDE interface 112, south bridge 110, PCI bus, and north bridge 104. The hard disk 114 must acknowledge to the memory 106 that data will be transferred and then waits a response from the memory 106. After the memory 106 responds to the request from the hard disk 114, the hard disk 114 begins to transfer data to the memory 106. When the hard disk 114 finishes the data transfer, the hard disk 114 has to send a stop signal to the memory 106 to acknowledge to the memory 106 that the data transfer is stopped, and waits a response from the memory 106.
Accordingly, the hard disk 114 has to wait for responses from the memory 106 before proceeding to the next tasks. Therefore, the hard disk 114 wastes much time to wait for the responses of the memory 106, which causes the time for signal transmission to be longer and the latency becomes longer. In order to transmit data effectively, a method for controlling a first in first out (FIFO) array is necessary.
According to the definition of a FIFO array, data prepared to transfer are first stored into a FIFO array composed of registers and data are read from the FIFO array according to the sequence of data written into the FIFO array. Therefore, the device for sending data can send data to the FIFO array first without waiting responses from the device of receiving the data. A FIFO controller controls the data-read/data-write operation. Therefore, the efficiency of transferring data and signals increases.
There are several methods for controlling a FIFO array. For example, the first method utilizes only a write pointer and a read pointer to indicate the status of the FIFO array. The second method just detects whether errors have occurred in the FIFO array but cannot determine whether the FIFO array is full or empty.
Although the two methods mentioned above can control the FIFO array, they can not use the write and read pointers effectively to indicate the status of the FIFO array. Therefore, the FIFO array can not be controlled effectively.
It is an objective to provide a method for controlling a FIFO array to facilitate data transmissions between a lower frequency domain and a higher frequency domain of a computer system. In addition to the write and read pointers, the method uses a flag to control the FIFO array. Moreover, a variety of status parameters are used for indicating the status of the FIFO array. By them, the FIFO array is easily and effective controlled for various situations.
As embodied and broadly described herein, the invention provides a method for controlling a FIFO array. The method uses a write pointer to indicate a write address, a read pointer to indicate a read address, a flag to indicate the status of the write pointer and the read pointer, and a number of status parameters to indicate the status of the FIFO array. The FIFO array comprises M addresses. (a) A determination is made as to whether a write data operation is performed; if so, pointing the write pointer points to the next address from the write address which the write pointer pointed to previously and then proceeding to step (c); otherwise, it proceeds to step (c). (b). A determination is made as to whether a read data operation is performed, if so, pointing the read pointer to the next address from the read address which the read pointer pointed to previously and then proceeding to step (c); otherwise, proceeding to step (c). (c). The status parameters are set corresponding to the status of the FIFO array currently.
In addition, the flag is set to a first value indicative of overflow of the FIFO array when the write pointer points to a maximum address of the FIFO array, the flag is set to a second value indicative of non-overflow of the FIFO array when the read pointer points to the maximum address of the FIFO array; and the FIFO array is controlled according to the read pointer the write pointers, the flag and the status parameters.
The write operation is performed when a first control signal of the lower frequency domain is received to indicate that a first data signal from the first device is pushed into the FIFO array.
The read operation is performed in response to the first control signal to generate a first output signal of the higher frequency domain according to the first control signal and phase signals of the higher frequency domain, as so to transfer the first data signal to the second device.
The write operation is performed when a second control signal of the higher frequency domain is received to indicate that a second data signal from the second device is pushed into the FIFO array; and
The read operation is performed in response to the second control signal to generate a second output signal of the lower frequency domain according to the second control signal and phase signals of the higher frequency domain, as so to transfer the second data signal to the first device.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.